Field of the Invention
Embodiments of the present invention relate generally to memory architecture and, more specifically, to an approach to improving drive strength in a static random access memory write driver.
Description of the Related Art
In computer systems, generally, and in graphics processing units (GPUs), in particular, there is widespread utilization of static random access memory (SRAM) circuits. A conventional SRAM cell consists of two inverters connected front to back and two pass transistors connected with output of inverters and bit line respectively. Specifically, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is connected to the input of the first inverter. The drain or source terminals of one pass transistor is connected with the output of the first inverter or bit line, and the drain and source terminals of another pass transistor are connected with the output of the second inverter and the complementary bit line. The gate terminals of both two gate pass transistors are connected to the word line. The output of one inverter represents the data bit, while the output of the complementary inverter represents the inverse of the data bit. To change the logic state (i.e. write a new value to the SRAM cell), a memory driver circuit overdrives one of the outputs to the opposite state. The overdrive action causes the driven inverter to change state, and the complementary inverter subsequently changes state to achieve the opposite logic state of both inverters
In conventional systems, the output of the inverter that is at the high level is driven to the low level. Each inverter includes a pair of field effect transistors (FETs). One P-channel FET (PFET) is connected to a supply voltage, and one N-channel FET (NFET) is connected to ground. The mid-points of both FETs are connected together. This arrangement is termed a complementary-metal-oxide-semiconductor (CMOS) circuit. In order to drive the output of the inverter to ground, the memory driver overpowers the PFET of the CMOS pair that forms the inverter. Therefore, the write driver that overdrives the inverter must be strong enough to pull the high level output below the threshold of the driven inverter, even though the P-channel device is trying to pull the output up. The strength, or current sinking capacity, of an integrated FET is proportional to the channel width of the device. Hence, N-channel FETs with the capability to overdrive an integrated P-channel device must have proportionally larger area.
Conventional SRAM memory cell macros are typically arranged in a matrix array. The data inputs to the SRAM cells, termed bit lines, are connected to all cells in a column. The row controls, termed word lines, are connected to all the cells in a row to select a particular row of cells in which data is stored. The circuit topology to realize the column selection and data writing of an SRAM cell consists of a pair of N-channel FETs connected in series that provide the conductive path between the pass transistor in memory cell and system ground. Thus, in a conventional SRAM driver arrangement, two NFETs in series form the path to ground that overdrives the upper PFET in the SRAM cell.
As described above, the area of the driving NFET must be proportionally larger than the upper PFET. Configuring two NFETS in series, then, further increases the area of the driver for times in order to achieve the same drive strength. Moreover, the series arrangement imposes a restriction on the minimum level of the supply voltage, as the serial structure reduces the driving strength, which reduces the write noise margin. The reduced write noise margin, in turn, limits the minimum supply voltage level. System voltage levels in present technology are decreasing to achieve increased speed and reduced power consumption. As systems migrate to lower supply voltage levels, the write noise margin of the SRAM is further reduced.
One drawback to the above approach is that the two series N-channel devices that overdrive the upper P-channel devices provide a weak drive that further weakens at reduced supply voltage levels. Further, tradeoffs to meet design margins that afford reliable operation essentially entail a choice between increasing die area excessively and imposing restrictions on the SRAM supply voltage reduction, thus limiting the scope of improvement in speed and power efficiency as technology advances.
As the foregoing illustrates, what is needed in the art is an approach to a drive circuit that improves the strength of an SRAM write driver while maintaining effective operation at reduced supply voltage levels.